Venice, Florida — Wafer stacking is becoming more ubiquitous for two principal reasons: shrinking space on the PC Board, and process requirements for mixed technology designs. A new product from Micro Magic aims at aiding the integration of various dies into one IC package. MAX-3D can combine distinct process wafers, and allows the designer to view, edit and connect the independent wafers into one 3D stack chip.
This design technique " known as "Through-Si Via Wafer Stacking" " allows distinct wafers to be stacked on each other, and connected internally (see figure 1). This results in chips with denser designs and higher performance. The technique increases signal integrity, reduces radiations that can interfere with the functioning of the circuit, and gives more freedom to designers by allowing them to use the appropriate manufacturing process for various functional blocks.
For example, a processor design in a 32 nm technology could be combined with a 65 nm memory and a 180 nm Analog device " on the same 3D chip. Furthermore, no changes need to be made to the foundry-supplied PDKs to incorporate these technologies in MAX-3D.
1. Example 3D Chip showing three wafer levels of different technologies combined in one 3D chip.
MAX-3D includes connectivity tracing, DRC checking and many other features found in Micro Magic's MAX layout editor. The product and its underlying technology have been in development for several years by one of the industry's leading experts " Dr Lisa McIlrath " Micro Magic's Chief Scientist. Through-Si Via 3D wafer stack designs are an extreme challenge for design tools. Current large 2D designs can crash many of today's layout editors. A 3D chip which connects several levels of 2D layouts multiplies the complexity of the design. MAX-3D has demonstrated its capacity by displaying and editing a design of 1.2 Trillion devices in real time.
MAX-3D is available for a 30 day trial to qualified IC design organizations. For more information, visit www.micromagic.com/max-3d.html