Many of us "old timers" remember the advent of logic (HDL) synthesis circa the late 1980s / early 1990s and its dramatic boost to productivity (prior to this, we were designing our chips as gate-level schematics).
Similarly, we also remember the disappointments associated with the initial forays into what was termed "behavioral synthesis". The problem was – and still is – the fact that although computers can perform vast numbers of mind-numbing calculations very quickly, they still can't match people when it comes to high-level decision making skills.
This is why Catapult C Synthesis from Mentor is proving to be so successful, because it combines sophisticated synthesis technology with human guidance and initiative. The Catapult C engine takes an un-timed ANSI C++ representation of the design and presents you with a graphical representation that identifies constructs like loops and allows you to state whether they should be unraveled, partially unraveled, or left alone. You can also specify if you wish to pipeline loops and other constructs, perform resource sharing on specific entities, and so forth.
A key point here is that all of these decisions are stored in the form of a side file – the original C++ representation remains untouched. This means that you can experiment with multiple "what-if" scenarios targeted toward different implementation platforms (an ASIC versus an FPGA, for example) or different architectures within the same platform.
When you are ready, you can press the "GO" button and Catapult C will generate the RTL that you subsequently pass to your downstream RTL Synthesis engine.
Catapult C has proven to be extremely successful, but there's always room for improvement. Hence the recent announcement by Mentor and Altera of an enhanced Catapult C design flow that enables users to implement complex DSP algorithms in high-performance FPGAs directly from industry standard ANSI C++.
The idea here is that if you have a statement like c += a*b; in your C++ source code (where a, b, and c are vectors), you may ultimately end up with an FPGA implementation in which a DSP block performs the a*b portion of the calculation and generates an intermediate result that we'll call i. This intermediate result may then be routed into a block of standard FPGA fabric, which performs the c+=i portion of the calculation. This implementation may end up with a maximum frequency (Fmax) of say 250 MHz.
The alternative is to call an accelerated library element in your C++ code. In the case of this particular example, we would use the following statement: c = Alt_Mac(a,b); This would ensure that the entire c += a*b; calculation is performed within one of the FPGA's DSP blocks, thereby increasing the Fmax to around 350 MHz.
On the one hand this is a step away from an "ideal" high-level synthesis solution that automatically does everything for us. On the other hand, this is a simple-to-implement and pragmatic solution that is claimed to deliver 50-to-80 percent DSP Fmax performance improvements, to provide a low-effort path to dedicated DSP hardware creation, and to offer a cost-per-channel advantage over expensive, power-hungry discrete digital signal processors for high-performance applications.
And the cool thing about all of this is that the latest-and-greatest Catapult C update release already includes these accelerated library elements. When you select a technology, you will see an accelerated library for that technology. In order to learn how to use these accelerated library elements, simply go to the Help menu, select the Tool Kits option, and locate the Accelerated Library tool kit. This will provide you with a wealth of documentation, including pre-built examples showing how this stuff all works.