Venice, Florida — The increased complexity and smaller feature sizes of today's chip designs make it more complicated to test manufactured ICs. New failure mechanisms are constantly emerging. Traditionally, most defects could be detected using stuck-at patterns generated by the ATPG tool using just a simple gate-level representation of the design. To maintain required defect per million (DPM) rates today, IC manufacturers must use test techniques that detect timing, layout and power-related defects. As a result, quality testing now requires the use of more fault models and time-consuming and error-prone importation of data from various design tools. Traditional ATPG tools have neither the performance nor the capacity to deliver the required level of test quality and turnaround time for nanometer ICs. EDA companies are introducing new capabilities in this field, and Magma Design Automation has unveiled Talus® ATPG and Talus ATPG-X with on-chip compression.
According to Geir Eide, Senior Product Manager of the Design Implementation Business Unit, these advanced automatic test pattern generation (ATPG) products enable designers to significantly improve test quality, reduce turnaround time and cut costs of nanometer (nm) ICs. By integrating Talus ATPG and Talus ATPG-X into the Talus physical design environment, Magma claims to offer the only IC implementation flow that provides true physically aware DFT.
Designed to concurrently target multiple fault models, Talus ATPG allows designers to improve test quality and turnaround time. It is fully integrated into Magma's Talus IC implementation system and leverages the unified data model architecture to efficiently access timing, layout, power and other design data that is not available to other ATPG tools. For example, this enables Talus ATPG to generate tests for subtle bridge defects and crosstalk. Access to the unified data model also allows Talus ATPG to support virtually all current fault-models and scale easily to support future models, and provides enhanced ease of use.
Talus ATPG is multi-threaded ATPG, enabling it to provide higher throughput than conventional tools. Talus ATPG-X includes on-chip compression, and Magma claims up to 40X reduction in test data volume. Talus ATPG also accurately diagnoses tester failures to find the logic and physical location of the defect. Diagnostic results can be passed on to Magma's Knights family CamelotTM and LogicMapTM products for correlation and failure analysis with the physical and electrical defects uploaded from the YieldManager® product in the same family.
As part of its push into the ATPG market, Magma has partnered with Inovys Corporation to ensure interoperability of Talus ATPG and Talus ATPG-X with the Ocelot tester. Magma has also collaborated with Source III to offer a direct path from Talus ATPG and Talus ATPG-X to variety of a test programs. Magma and its partners are also developing validated feedback paths from testers to the diagnostic capability in Talus ATPG that will allow designers to further analyze the causes of device failure. With a foundation in the IEEE 1450 Standard Test Interface Language (STIL) and through its collaboration with Inovys and Source III, Magma is working to improve test quality, streamline the test flow and reduce test costs.