Hsinchu, TaiwanRambus Inc. has introduced a memory controller interface for industry-standard DDR3 DRAM.
The fully integrated hard macro cell provides the physical layer (PHY) interface between the controller logic and DDR3 or DDR2 DRAM devices for data rates of up to 1600 MHz. Engineers can seamlessly integrate the DDR memory controller cell into their customer-owned tooling (COT) or ASIC.
The Rambus DDR3 memory controller interface cell is designed to accommodate a broad range of applications including PC main memory, consumer electronics, servers, workstations, and network communications.
The Rambus DDR3 memory controller incorporates Rambus' FlexPhase timing adjustment circuits for precise on-chip data alignment with the clock, as well as calibrated output drivers and on-die termination.
Download the product brief by clicking here.
Rambus Inc., 1-650-947-5000, www.rambus.com