Cambridge, England XJTAG has released version 2.0 of its XJTAG boundary scan development system that offers several enhancements that simplify and speed up printed-circuit-board (PCB) debug and test.
Used by board developers and manufacturers to debug, test and program complex ball grid array (BGA) populated PCBs and systems, the XJTAG 2.0 offers a slew of new features including automated JTAG chain discovery and set-up, a built-in netlist explore that provides a simple interface to view the connectivity between devices on the board, optimized memory test, and real-time design for test (DFT) coverage tracking.
The 2.0 version also includes an extended library of device-centric test scripts, improved integration with LabVIEW, and support for Xilinx's Virtex-5 FPGA System Monitor to enable customers to check power supplies or perform overall thermal management using the JTAG port on the 65-nm Virtex-5 FPGAs.
XJTAG now also offers a drag-and-drop interface that automates the JTAG chain discovery and set-up process. The developer simply connects the computer to the unit under test via the USB2.0 XJLink hardware module; creates a new project, and adds the target board. The XJTAG system then detects the scan chain and matches the JTAG device codes to their respective BSDL files, as well as identifies ground nets and makes intelligent suggestions about other components. This intelligent set-up facility enables the board developer to quickly categorize all of the non-JTAG or cluster devices in the circuit, said XJTAG.
XJTAG enables engineers to test a high proportion of the circuit (both boundary scan and cluster devices) including BGA and chip-scale packages such as SDRAMs, Ethernet controllers, video interfaces, Flash memories, FPGAs and microprocessors.
XJTAG 2.0 will be unveiled at Productronica (Area A1/Booth 448), in Germany, November 13-16, 2007.
XJTAG: +44 (0) 1954 213888 or e-mail firstname.lastname@example.org, www.xjtag.com