This is rather interesting. Over the years, FPGA vendors have either developed their own microprocessor cores (for example the Nios from Altera and the MicroBlaze from Xilinx) or they've ported existing offerings such as ARM cores from the standard cell ASIC domain.
In the latter case – that of an ASIC core being ported to an FPGA – one analogy that springs to mind is that of a movie created for the "big screen" subsequently being re-formatted and presented on television.
But when was the last time you heard of a "made-for-television" movie being presented at your local cinema? Well, that's essentially what's happened, because Altera and Synopsys have collaborated to take Altera's Nios II soft processor core and make an ASIC-optimized version available for licensing through Synopsys' DesignWare Star IP Program.
Although this may seem to be a somewhat surprising development at first, it actually makes a lot of sense. The Nios II has now reached a significant level of adoption around the world. Altera says that their Nios II customer base includes more than 5,000 electronics manufacturers, including the world's top electronics OEMs.
Many of these manufacturers start deploying a new product based on an FPGA implementation. If the product starts to perform well in the market, the next step might be to migrate the design to Altera's HardCopy structured ASIC. Now, if the product starts to sell "gang-busters", this new offering enables Nios II users to migrate their designs to standard cell ASICs.
The idea behind Synopsys' DesignWare Star IP program is to provide designers with access to high-performance, high-value processor and DSP cores developed by leading Star IP providers. Utilizing its core competencies in design-for-reuse, intellectual property (IP) packaging methodologies, and design flows, Synopsys will provide a configurable, fully synthesizable version of the Nios II processor core optimized for ASIC implementation. Designers will be able to use the core in the foundry and process technology of their choice. By combining this reusable core with Synopsys' portfolio of tools, support, design services, and additional key system-on-chip IP building blocks, Synopsys offers designers a robust solution for realizing their Nios II processor-based ASICs and ASSPs.
The synthesizable version of the Nios II processor core is expected to be available from Synopsys in the first quarter of 2008.