London, OntarioMicrotronix has launched the video LVDS SerDes transmitter/receiver IP core targeted at high resolution 1080p 100/120 LCD panel display systems.
The core is aimed at enabling a wide variety of video host systems interface to flat-panel displays. The transmitter and receiver cores support both 28 bit (8 bit RGB) and 35 bit (10-bit RGB) parallel data configurations using either four or five LVDS serial channels. Transmitter and receiver modules can be cascaded to create dual and quad LVDS links supporting display panel resolutions up to 1080p at 120-Hz and beyond.
The Microtronix Video LVDS SerDes transmitter/receiver IP core supports both Cyclone II and III devices. IP core development is supported with the Microtronix ViClaro III HD video dsplay panel IP development platform and a set of multi-port SDRAM memory controller IP cores.
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Microtronix, 1-519-690-0091, www.microtronix.com