Venice, Florida — Mentor Graphics Corporation has released support for hardware description language (HDL) generated by MathWorks Simulink HDL Coder in the Mentor Graphics Precision® suite of advanced synthesis products. This capability enables designers to transfer VHDL and Verilog generated by Simulink HDL Coder into the Precision Synthesis tool directly to generate an optimized netlist implementation for field programmable gate array (FPGA) designs. All mutual customers using Precision 2006a release or newer with Simulink HDL Coder can benefit from this flow.
The MathWorks and Mentor Graphics have collaborated on this flow to assure interoperability. Simulink HDL Coder generates bit-true, cycle-accurate, synthesizable Verilog and VHDL code from Simulink models, Embedded MATLAB code, and Stateflow charts. The integration is another significant step in developing "correct by construction" design methods that connect architectural design to silicon implementation. The need for manual intervention by designers to link the product of architectural design to a layout ready netlist has been one of the obstacles to the growth of the ESL market in the past.
Precision Synthesis is available at a starting price of $20,200 (USD).