Venice, Florida — Cadence Design Systems, today announced that
new technologies have been integrated into the Cadence® Incisive®
Enterprise verification family that enable engineering teams to address increasingly
complex chip design. Incisive technologies now offer support for the newly developed Open Verification Methodology (OVM), a new aspect-oriented generation engine,
and the second generation of Cadence transaction-based acceleration (TBA) with native
support of multiple testbench languages and numerous productivity enhancements.
The new aspect-oriented generation engine leverages aspect-oriented programming (AOP) architected testbenches to improve performance and scalability. The Cadence Incisive Specman®, Incisive Enterprise Simulator, and the Incisive Palladium® and Xtreme® hardware acceleration/emulation systems have all been enhanced as a result of this release.
New Aspect-Oriented Generation Engine
The e language supports aspect-oriented programming, a type of object-oriented programming capability that allows customization by users to adapt to specific verification requirements. The capability now offers improved stimulus generation ability to users executing complex, aspect-oriented sequences against large designs. The new engine increases performance by nearly five times for e-based verification environments. The feature is available in the Incisive Enterprise Simulator and Incisive Specman products. According to Michal Siwinski, Product Marketing Group Director,
Advanced Verification at Cadence, the feature offers up to five times increase in performance for users of the e-based verification environments.
Aspect-oriented programming can help in various areas, but it is most useful to verification engineers in improving "logging" which is frequently used in distributed applications to aid debugging by tracing method calls. A good reference to aspect-oriented programming can be found at AOP.
Support for Open Verification Methodology
As design complexity escalates, building and debugging verification testbenches
becomes increasingly difficult. This past August, Cadence and Mentor launched the Open Verification Methodology (OVM) initiative to improve overall team productivity and greater predictability in the verification process. The mixed-language Incisive Enterprise Simulator now supports OVM and its underlying class library, reducing the time it takes to create SystemVerilog verification environments and ensuring code portability and reuse. In addition, enhanced class-based debug utilities help manage the complexity of object-oriented testbench code. A new multi-language verification builder utility enables users to leverage existing templates, configure verification IP and accelerate early testbench development.
Second-Generation Transaction-Based Acceleration
With this release the Incisive Enterprise verification family delivers new capabilities to improve the productivity for system-level verification using Xtreme and Palladium hardware acceleration/emulation systems. A new version of Cadence TBA is compliant with the Accellera SCE-MI 2.0 draft standard, ensuring automation, ease of use, and platform portability while delivering high performance.
The SCE-MI standard allows improvements to high speed transaction-level verification between different hardware and software simulation and emulation systems as well as models portability between different verification acceleration tools. Work on the SCE-MI standard was started by Accellera following a proposal by Ikos Systems in 1999 and resulted in the SCE-MI 1.1 standard in 2005. According to Ran Avirun, Product Marketing Group Director System level design and validation at Cadence, the 2.0 draft standard shold be ratified by Accellera's board of directors by June 2008.
TBA 2.0 helps design and verification teams reduce their verification time by providing new infrastructure and guidelines to support reusable accelerated verification environment. The new TBA version combines methodology and product delivery, with a number of features that simplify the creation and debugging of transaction-based verification environments and verification IP, including: a native multi-language transaction-level modeling interface, automatic variable-length messaging, constraint randomization, automated transaction-level recording and powerful signal/transaction-level debugging capabilities.
Incisive Enterprise Simulator 6.2, Incisive Specman 6.2 and TBA 2.0 enabled
Incisive Palladium and Incisive Xtreme are currently available.
Cadence, Mentor team on SystemVerilog verification, and
Synopsys was not invited to join SystemVerilog OVM initiative