The folks at Altera Altera say they have achieved DDR3 memory interface speeds in excess of 1067 Mbps with their Stratix III FPGAs. This higher memory bandwidth enables new communications, computing, and video processing applications that were either previously impossible or required doubling the number of memory banks.
Altera's Stratix III FPGA family is claimed to be the industry's only FPGA to demonstrate full compliance to the JESD79-3 JEDEC DDR3 SDRAM standard, including the performance-critical read/write-leveling specification for maximum system performance.
Designed to address the benefits of DDR3 memory, Altera's Stratix III family is claimed to be the only FPGA in the industry to include read and write leveling, I/O delay for DQ de-skew, dynamic on-chip termination, and the use of a reconfigurable phase-locked loop (PLL) to compensate for voltage and temperature variations.
In addition, Altera's Quartus II software version 7.2 includes a DDR3 PHY wizard and controller intellectual property (IP), which substantially simplifies high-performance memory interface design by automatically adapting to DIMMs from a variety of memory suppliers.
Altera Stratix III FPGAs featuring DDR3 memory bandwidth capabilities of 533 MHz are available now. To learn more about Altera's Stratix III FPGAs, visit www.altera.com/stratix3. To learn more about how easily FPGAs can interface with DDR3 SDRAM, visit Altera's webcast by Clicking Here.