One of the ploys of many an EDA company releasing a technology is to call the technology "Open." Technologies such as OpenVera, Open MAST, Open Silicon, Open SystemC and so forth spring immediately to mind.
Unfortunately, "openness" is an imprecisely defined term, and much technology touted as open is all too often encumbered by legal requirements impeding its truly open use. An EDA engineer might therefore be tempted to consider the recent release of Cadence's and Mentor Graphics' "Open Verification Methodology" (OVM) merely more of the same.
But this time, that's not the case. OVM is a truly open SystemVerilog class library and methodology package that can be used free of any restraints imposed by either Cadence or Mentor. This true openness, as well as the underlying technology itself, will dramatically help in fulfilling the original promise of SystemVerilog, especially when contrasted with its closed alternative.
To see how the openness of OVM benefits the entire industry, consider the case of an EDA startup armed with an idea that could potentially revolutionize functional verification. Because it uses OVM, the startup doesn't need to reinvent the SystemVerilog wheel, but can instead use OVM as a product enabler without any restrictions whatsoever, even if its new product will directly compete with current Cadence and Mentor verification products. This facilitates the introduction of new EDA technology and is clearly a win for the entire industry, allowing verification startups to focus on their "secret sauce," which is a clear recipe for industry growth.
In much the same way, an internal CAD group at a system or semiconductor company may make the decision to acquire commercial SystemVerilog solutions instead of developing its own internal tools or libraries. But, because SoC designs often contain complex blocks written at multiple levels of abstraction, as well as blocks written in multiple languages, a company-specific customization of the base commercial SystemVerilog solution might well be needed.
OVM allows such a CAD group to freely fine-tune vendor-provided OVM class libraries and methodologies to meet its company's specific requirements. By using OVM, the company will be able to internally and externally distribute the source code resulting from this fine-tuning, a solution that incorporates the best of both worlds: a robust commercial solution that can be freely extended and redistributed to solve evolving design and verification issues.
User-company executives reticent to depend on a single EDA vendor will be glad to find that OVM provides seamless interoperability between the IEEE 1800 SystemVerilog supporting platforms of two of the three major EDA vendors. These executives will no longer be forced to make the choice between three incompatible sets of base class libraries and methodologies, but can now choose a solution supported by two thirds of the simulation seats worldwide. If Synopsys decides to adopt OVM, that proportion could rise to nearly 100 percent.
The openness of OVM is found to contrast sharply with the closed nature of its competition in the SystemVerilog methodology area with a look at the alternative's license under "Other rights and restrictions." It is difficult to find any rights granted in this section. Rather, three clauses begin with the words "You may not . . ." and are followed by a fourth clause admonishing licensees that their licenses will be summarily terminated if any of the preceding conditions are violated. This is exactly the sort of anti-openness that has kept SystemVerilog from fulfilling its original promise.
By way of comparison, the Apache 2.0 license, under which OVM is registered, mentions termination only in reference to cases in which one licensee institutes patent infringement proceedings against another licensee. In other words, license termination is invoked only when any licensee attempts to restrict the terms of the license. In all other cases, licensees of OVM may use the product however they wish without reporting to either Mentor or Cadence, so long as all copyright notices are maintained and all derivative works are distributed under the same open license.
There is presently a measure of "openness fatigue" permeating the industry, but that's because the term "open" has been far too often applied to products and organizations that are far from open in significant ways. Happily, that's not the case with OVM, the joint effort of two business competitors who are providing a completely open solution for the benefit of the entire industry. Will the introduction of this robust, interoperable SystemVerilog solution help fulfill that language's original promise?
The case is open-and-shut.
Stanley Krolikoski has been deeply involved in standards activities throughout his 25+ year career in the EDA industry. He is currently Group Director, Standards and Interoperability at Cadence.