The folks at Mentor Graphics have announced the availability of a new Electronic System Level (ESL) hardware design and verification flow featuring Mentor's Catapult C Synthesis tool and the SLEC sequential equivalence checker from Calypto Design Systems.
Proven during trials at customer sites throughout the world and recently by STARC, the integrated flow is effective at synthesizing high-quality designs from pure ANSI C++ to RTL, and formally verifying that the resulting RTL design is functionally correct. These customer results validate the Mentor/Calypto design flow, and indicate its readiness for broad production usage by companies using ESL methodologies for hardware design.
The folks at Mentor say that these two "best-in-class" design tools offer a superior, integrated solution for ANSI C++ synthesis and verification. The Catapult C Synthesis tool enables hardware designers to create optimized RTL descriptions 10-100x faster than manual design methods. Calypto's SLEC comprehensively verifies that RTL designs are functionally equivalent to system-level models without testbenches or assertions. SLEC uses sequential analysis techniques to verify Catapult C's RTL output functionally matches the original ANSI C++ source. The integration of the Catapult C Synthesis tool and SLEC increases designer productivity by providing users with a fast, exhaustive, vector-less design and verification methodology.
With this integration, Catapult C Synthesis tool users can automatically generate RTL from a pure ANSI C++ description, and then create the setup scripts to launch the SLEC verification environment. This allows users to verify equivalence between the pure ANSI C++ and RTL descriptions quickly as well as verify additional design optimizations before handoff for final integrated circuit implementation.