The R2A60281LG integrates 2G (GPRS/EDGE) quad-band
(850MHz/ 900MHz/ 1.8GHz/ 1.9GHz) and 3G (W-CDMA) quad-band (800MHz/1.5 GHz/ 1.7 GHz/ 2 GHz) functionality into a single chip. It also supports High-Speed Downlink Packet Access(HSDPA) categories 7
and 8 for data downloads at speeds up to max. 7.2 Mbps as well as High Speed Uplink Packet Access (HPUPA). The chip is built in 0.18 micrometer BiCMOS technology.
The transceiver includes the low-noise amplifiers (LNAs), a loop filter circuit, and HPA controls. A filter supporting CDMA2000 attenuates wavelengths outside the desired frequency band, reducing susceptibility to RF interference. Also, a 312Mbps (max.) digital interface function supports 3G DIGRF operation, offering the A/D and D/A conversion functions formerly handled by an
analog baseband processor. This interface enables high-speed exchanges of In-Phase/Quadrature-Phase (I/Q) and control data with a digital baseband processor, for quick transfers of large data volumes.
The R2A60281LG 2G/3G dual-mode RF transceiver supports the 1.5GHz band under the specifications newly standardized by the Third Generation Partnership Project (3GPP). The device measures 7x7x0.6 mm and is housed in a 120-pin LGA package. Samples are priced at $9 and will be available in March 2008.
For more information, visit www.renesas.com.