The folks at Cadence Design Systems and Mentor Graphics have announced an enhanced release of the source-code library and user documentation for the Open Verification Methodology (OVM), the industry's first open, interoperable SystemVerilog verification methodology.
These enhancements are said to be the result of feedback from the growing user community at the OVM World site (www.ovmworld.org). To further support these users, Mentor Graphics and Cadence – joint developers of the OVM – are launching a series of worldwide activities.
Distributed under the standard open-source Apache 2.0 license, the OVM source code, usage examples, and documentation may be downloaded free of charge from OVM World. In its first month, this site has gathered more than 1,700 registered users representing more than 700 companies. Registration allows users to download and to participate in a lively online forum in which they can share information, ask questions of OVM technologists, and propose ideas for enhancements to the library and methodology.
Users will be able to learn more about the OVM and its applications at the Design and Verification Conference and Exhibition (DVCon) in San Jose Feb. 19-21. OVM World activities sponsored by Mentor Graphics and Cadence include a Tuesday morning tutorial, a Wednesday evening cocktail reception, a Thursday morning technical session, and a Thursday lunchtime user panel. Complete details on DVCon events may be found at www.ovmworld.org/tradeshows.php.
Users will also have the chance to meet at a series of worldwide seminars over the upcoming months. These free seminars, jointly sponsored by Cadence and Mentor Graphics, will be held at more than a dozen locations in North America, Europe and Asia. A complete list of locations and dates with registration instructions may be found at www.ovmworld.org/seminars.php. A follow-up OVM World event is planned for the 2008 Design Automation Conference (DAC) to be held June 8-13 in Anaheim, Calif.
Open Verification Methodology
The Open Verification Methodology, based on IEEE Std. 1800-2005 SystemVerilog standard, is the first open, language-interoperable, SystemVerilog verification methodology in the industry. It provides a methodology and accompanying library that allow users to create modular, reusable verification environments in which components communicate with each other via standard transaction-level modeling interfaces. It also enables intra- and inter-company reuse through a common methodology and classes for virtual sequences and block-to-system reuse, and full integration with other languages commonly used in production flows.