The folks at Lattice Semiconductor say that they will be demonstrating a wide range of complete FPGA-based design solutions – including PCI Express, SMPTE video, and their LatticeMico32 embedded RISC microprocessor running the uClinux Real Time Operating System (RTOS) – at the Embedded World Conference and Exhibition, February 26-28, in Nürnberg, Germany. The Lattice exhibit is located in Hall 12, Stand 350.
Lattice will provide live demonstrations of its PCI Express endpoint capabilities running on its evaluation board. The board utilizes a soft PCI Express core (available in either ×1 or ×4 configurations) programmed into a LatticeECP2M low-cost FPGA with on-chip 3.125 Gbps SERDES blocks. The folks at Lattice say that LatticeECP2M devices provide the only FPGA-based PCI Express solution priced below $10.00 in high volume.
Lattice also will demonstrate its SMPTE capabilities using the LatticeECP2M devices. The Society of Motion Picture and Television Engineers (SMPTE) has defined the Serial Digital Interface (SDI) family of standards. These standards define the physical interface and related circuitry needed to transport uncompressed digital video over 75-ohm coax cable.
In addition, Lattice will showcase its implementation of the uClinux OS using a LatticeMico32 evaluation board. The LatticeMico32 core is Lattice's 32-bit embedded RISC soft microprocessor, available to customers through a unique open source license agreement. The LatticeMico32 processor also is supported by Micrium's µC/OS-II and the TOPPERS µITRON operating systems.
Lattice also plans to display design solutions using boards from its business and IP core partners, including display controller and Industrial Ethernet solutions.
About LatticeECP2M FPGAs
The folks at Lattice say that their LatticeECP2M FPGAs are an innovative response to the broad range of customers who have been clamoring for low-cost SERDES capability for chip-to-chip and small form-factor backplane applications. They also say that the LatticeECP2M family maintains all of the compelling features of the 90 nm LatticeECP2 family that are required for high-volume, cost-sensitive applications, while dramatically increasing memory capacity (ranging from 1.2 Mbits to 5.3 Mbits) and DSP resources (ranging from 24 to 168 multipliers).
The five devices in the series, ranging in size from 19K to 95K lookup tables (LUTs), provide an inexpensive alternative for implementing PCI Express, Ethernet, Serial RapidIO and CPRI/OBSAI interfaces. A flexible PCS layer that includes 8b/10b encoding, an Ethernet link state machine, and rate matching circuitry also are built onto the chip. The SERDES/PCS combination is designed to support today's most common packet-based protocols, including PCI Express, Gigabit Ethernet, Serial RapidIO and wireless interface standards (OBSAI and CPRI).
About the LatticeMico32 embedded microprocessor
The LatticeMico32 IP core is a 32-bit soft microprocessor optimized for Lattice Field Programmable Gate Arrays (FPGAs). Lattice has released the Hardware Description Language (HDL) code of the microprocessor core and various peripheral components generated by the LatticeMico32 System, along with selected tools, in an open source format that provides visibility, flexibility and portability.
The heart of the product is the LatticeMico32 System development tool suite, which provides a fast and easy way to implement microprocessor designs from platform definition to software development and debug. This flexible microprocessor finds application in a wide variety of markets including communications, consumer, computing, medical, industrial and automotive.