Venice, Florida — Mentor Graphics Corporation has introduced the Questa® Multi-view Verification Components product and the inFactTMintelligent testbench automation tool " two new solutions that use breakthrough technologies to speed up verification and drastically improve verification coverage of today's SoC (System on Chip) designs.
The Questa functional verification platform combines provides comprehensive verification capabilities. Assertion-based Verification (ABV), intelligent testbench automation, Multi-view Verification Components (MVC), and Coverage-driven Verification (CDV) are supported natively by the Questa platform's high-performance assertion engine; a modern, high-performance constraint solver; and extensive functional coverage features, including verification management leveraging the Unified Coverage Database (UCDB). Verification of low power design functionality can be proven in an RTL environment with power-aware functional verification. This full set of advanced verification functionality is enabled by a flexible Open Verification Methodology (OVM) that delivers unrivaled language and feature support in any design and verification flow.
Lowering the Barriers to Mixed-abstraction Verification
The complexity of today's SoC verification environments often requires designers to spend valuable time building and verifying multiple and usually incompatible verification models of a single block to support system-level, TLM-level and RTL-level verification. This lack of consistency prevents teams from easily moving up and down in abstraction and maximizing verification effectiveness. Mentor's unique Questa Multi-view Verification Components (MVC) product can connect to any level of abstraction from system to gates " ensuring consistent model behavior and giving the verification team more options to improve performance and increase coverage.
Mentor uses synthesis technology to automatically produce model wrappers that provide the necessary interface signals and timing required to normalize the abstraction levels of the various models. This avoids possible sources of errors due to manual translation and saves project time. Figure 1 shows an architectural rendering of the resulting test environment.
1. An architectural view of the MVC solution.
Algorithmic Stimulus Generation Gets to Coverage Faster
Once verification components are available, designers need to create the stimulus to drive the models. Creating test stimulus by hand is one of the most time-consuming steps in the verification flow. Using advanced algorithms to synthesize non-repeating stimulus, Mentor's new intelligent testbench automation technology, inFact, simultaneously reduces test creation time, minimizes redundant testing, and stimulates more of the design " resulting in more bugs found and dramatically faster time to coverage. The new capability is based on compiler development technology that allows to parse test requirements and goals using Backus Naur Form (BNF) parsing technology. A pictorial representation of possible results can be seen in Figure 2.
1. inFact supports a number of testing techniques.
Accelerating Adoption with OVM
Combining these new tools with the Questa functional verification platform, the Open Verification Methodology (OVM), and standards like SystemVerilog, Mentor is opening the doors to broader adoption of breakthrough verification flows.
"The next major step in advanced functional verification happens when manual, time-consuming tasks are replaced with new levels of automation and tool intelligence," said Robert Hum, vice president and general manager of Mentor Graphics Design Verification and Test division. "With the Questa functional verification platform, we believe we're on the right track " not only from a technology point of view, but also in terms of providing a complete, comprehensive solution."
"The exploding cost of embedded software design puts increased pressure on SoC budgets. Since there is no immediate answer to the software crisis, management is now focused on the high cost of verification," stated Gary Smith, founder and chief analyst for Gary Smith EDA. "Throwing engineers at the problem is not an acceptable answer whether they be in the US, Europe or India. The target is to bring verification costs down to 35% of the total hardware design cost, and we can only do that through automation. The intelligent testbench is the missing ingredient in today's verification flow. At DAC 2007 we saw three start-ups addressing the problem. Today Mentor announces their intelligent testbench tool. Help is on the way."
Pricing and Availability
inFact is available now and Questa MVCs will be available in Q2 2008. Pricing starts at $25,000.