MANHASSET, N.Y. Tela Innovations is unveiling a computational lithography technology that addresses the challenges of fabricating 45 nm and smaller chips, basing its approach on on-grid, straight line, one- dimensional layout structures.
Tela has reached the end of a three-year development stage, and expects to test 45-nm chips for Qualcomm next month.
As process technologies advance into "sub- wavelength" range--where process dimensions are shrinking faster than wavelengths--changes in design styles are needed to improve manufacturability and reduce costs. That means the industry is moving toward more restrictions on layout interactions.
At 32 nm and below, double exposure and double patterning technologies will be used. At that point, Tela executives predict, a design approach will be needed that enables patterns on a single mask to be efficiently separated into two masks.
Tela's executive team includes co-founders CEO Scott Becker and CTO Dhrumil Gandhi, both former executives at Artisan Components. Mike Smayling, senior vice president for product technology, was a Texas Instruments fellow and CTO at Applied Materials.
"Our solution is straightforward to implement and works within standard EDA flows, in mask preparation and with leading semiconductor manufacturing processes," Becker said. "We believe it represents the next generation design style necessary to continue scaling in an economically and technically efficient manner."
Tela said its pre-defined physical topologies can be used in logic, embedded memory, analog and I/O functions. When synthesized and routed as part of an overall design, Tela claims its solution enables a lithography-optimized layout.
"The Tela solution consists of regular-patterned, pre-defined topologies consisting of straight lines with no bends, jogs or shoulders," said Neal Carney, vice president of marketing.
"The approach provides the designer and manufacturer with a fixed set of interactions between shapes, reducing the unpredictable variation induced by more random layout methodologies," Carney added. "The resulting logic blocks have a lower k1 lithography [resolution] limit."
According to Robert Socha, imaging scientist at lithography tool maker ASML, the k1 factor is reduced by optimizing the entire lithography process, including IC design, the mask, the scanner and the photoresist. At low k1, the entire lithography process is combined so that changing one part of the process affects other parts. In order to achieve the lowest k1 resolution limit during production, understanding the impact of each part of the lithography process on imaging is essential.
"Tela's approach looks promising in its ability to provide a structured design style while meeting our design objectives," said Nick Yu, Qualcomm's vice president of engineering.
Tela's Carney said early testing "resulted in a 15 percent area reduction and a 2.5x reduction in leakage using a 45-nm process." He added that the cells and resulting blocks were successfully implemented using existing production design flows and tools.
Tela's technology is delivered as a physical design representation (GDSII). Tela's said it initial focus is on applying its solution to standard cell logic followed by embedded SRAM memories, analog and I/O. The company's strategy is to partner with customers' IP development teams to enable Tela's proprietary solution to be adopted for production IC design.
Details of the technology will be disclosed in two technical papers on Thursday (Feb. 28) at the SPIE Advanced Lithography Conference.
Tela Innovations is privately held, with funding from Sand Hill Finance Co. and Teton Capital, Intel Capital, AsiaTech Investment and Western Technology Investment. Its board of directors includes Donald Lucas, former Cadence Systems CEO Ray Bingham and EDA entrepreneur and investor Jim Hogan.