The folks at eASIC, a provider of zero-mask charge ASIC devices, recently announced the first phase of a worldwide program that is aimed at ushering in a new era of affordable silicon customization.
The first step in this far-reaching program is to assist companies that are hampered by high FPGA unit costs to set more aggressive market pricing for their end products. The initial targets of this FPGA cost reduction program are the low density FPGAs that are primarily used in consumer and multimedia applications.
"Silicon customization was once affordable to many, but as the costs of ASIC design, verification and manufacture increased, ASICs became a viable platform for only the privileged few. Hence, the number of ASIC design starts per year has continued to decrease. Despite earlier promises, FPGAs have not been able to fill this gap due to their very high unit cost and high power consumption," said Jasbinder Bhoot, Senior Director of Marketing at eASIC.
In order to address this, the eASIC program is intended to bring back an era of mass silicon customization, thereby leading to "many-designs-per-engineer" as opposed to "many-engineers-per-design."
eASIC's Nextreme family of zero mask charge and no minimum order ASIC devices provides designers with the low cost benefits of traditional ASIC devices, combined with a rapid design cycle and only a four- to five-week silicon turnaround time.
Program overview and pricing
The cost reduction program requires zero investment in tools. Customers can provide eASIC with eASIC-ready RTL. eASIC's unique technology allows a four to five week silicon turnaround time. The 1000 unit promotional price for eASICs Nextreme NX750 device is only $14.95 per unit.
The NX750 is capable of replacing the XC3S1600E, XC3S1200E, XC3S1000, XC3S1500, XC3S1000, XC3S2000, XC3S4000 and XC3S5000 from Xilinx, and the EP3C16, EP3C25, EP3C40 and EP3C55 from Altera.