Venice, Florida — Synopsys, Inc. has released its new Design Compiler® Graphical synthesis product aimed at helping RTL designers avoid wire-routing congestion problems that typically occur during detailed route. Design Compiler Graphical predicts circuit congestion "hot spots" early in the design flow, provides designers with visualization of the congested circuit regions and performs synthesis optimizations to minimize congestion in these areas. The ability to predict, visualize and alleviate routing problems prior to physical implementation reduces iterations between synthesis and place-and-route, and can significantly lower project time, effort and cost. Even if a design meets all the performance specifications, congestion can be severe enough to make it very difficult to successfully route the design, leading to longer design cycles and more iterations between synthesis and place-and-route.
The new Design Compiler Graphical product circumvents these iterations. First, it provides congestion reports and visualization to assist designers in identifying congested regions in a circuit. Second, it employs optimization techniques to synthesize a design with significantly less congestion, thereby creating a better starting point for physical design. The ability to first estimate and then prevent routing congestion problems early in the design phase produces a more predictable, streamlined design flow from RTL synthesis through physical implementation that can shave weeks off project schedules.
Design Compiler Graphical is available today as an add-on to DC Ultra.