Venice, Florida — Synopsys, Inc. today unveiled Zroute, a new multi-threaded router fully integrated into IC Compiler. The new engine has been developed from the ground up to take full advantage of the newest multi-core microprocessor architectures and to solve DFM challenges in IC design.
Zroute's architecture incorporates native support of soft rules to enable "lithography-friendly" routing and avoid manufacturing problems. By simultaneously considering the impact of manufacturing rules, as well as timing and other design goals, Zroute improved manufacturability. Zroute was developed to take advantage of multi-core compute platforms. Utilizing a combination of new routing algorithms and multi-threading technology, Zroute has shown a speed increase of more than 10X on some customer designs running on quad-core machines.
Zroute is incorporated as a standard feature in IC Compiler, offering an alternate choice for routing technology which can be enabled by customers as required. Zroute was specifically developed as a concurrent optimization router to deal with future technical challenges. Rather than addressing these issues later in the flow, Zroute's strategy reserves routing resources for yield optimizations at each step of the flow, enabling their impact to be considered simultaneously with other cost functions. Additionally, Zroute is
multi-threaded at each of its internal steps.
"Zroute is an excellent example of Synopsys' investment in R&D to help our customers stay ahead of the technology curve. Anticipating future requirements, we set out to develop a new router that not only could address the emerging issues of DFM, timing, and other design goals, but could do it much faster executing transparently on the new multi-core processors," said Antun Domic, senior vice president and general manager, Synopsys Implementation Group.
Zroute will be in limited production availability as a standard feature in IC Compiler in June 2008.