GenevaSTMicroelectronics' latest member of its SPEAr family of configurable SoCs is manufactured using 65-nm process technology, yielding increased density, performance and power-reduction features.
By transferring the SPEAr family to 65-nm process technology, the SPEAr Basic device is capable of integrating an advanced ARM926EJ-S processor core with two 16k memory caches, running at 333MHz, for data and instructions and up to 300,000 gates (ASIC-equivalent) of embedded configurable logic.
The SPEAr Basic device addresses a wide variety of embedded applications, including entry-level printers, fax machines, digital photo frames, Voice-over-IP and other equipment.
The SPEAr Basic provides memory interfaces supporting LP-DDR and DDR2 memories and a large connectivity-IP portfolio, including Fast-IrDA interface, Ethernet MAC, three USB 2.0 ports with embedded PHYs, UART, SPI, I²C, up to 102 fully programmable GPIOs and a total of 72 Kbytes of SRAM and 32 Kbytes of Boot ROM.
High printing performance is enabled through a full set of image-pipeline accelerators, from color-space conversion to raster-file generation, a rotation engine, a hardware JPEG codec, an LCD controller (up to 1024x768, 24-bits per pixel) and a SDIO/MM card interface.
Additional features include a 10-bit A/D converter, a crypto accelerator based on ST's proprietary C3 IP, a Flexible Static Memory controller (NOR/NAND Flash and SRAM), TDM (Time-Division Multiplexing) and SLIC (Serial Link and Interrupt) controllers and a camera interface, providing unprecedented scale of integration and flexibility.
Pricing: $6 in quantities of more than 20,000 pieces.
Availability: Samples are available now, with volume production set to start by the end of Q3 2008.
Datasheets: Click here.