Anaheim, California — Cadence Design Systems, Inc. and UMC have announced the availability of a Common Power Format (CPF)-based low-power reference design flow targeted to the UMC 65-nanometer process. This reference flow enables customers to achieve low-power designs when used with UMC's Low Power Kit, which includes CPF-enabled libraries and other intellectual property.
This 65-nanometer low-power reference design flow uses UMC's "Leon" test chip as the reference design. Leon is an open source 32-bit RISC microprocessor core with other complex elements including SRAM. The Leon chip was partitioned into multiple voltage domains using the Cadence Low-Power Solution for design, verification, implementation and analysis. The UMC 65-nanometer low-power reference design flow highlights key capabilities of the Cadence Low-Power Solution.
This reference flow package includes design resources, implementation scripts, an application note and a comprehensive workbook. This 65-nanometer Low Power reference design flow is slated for availability in July 2008 through UMC sales.