PORTLAND, Ore. The world''s lowest-power integrated circuit consumes 10 times less juice when active and better than 30,000 times less power in sleep mode, according to its developers at the University of Michigan. The so-called Phoenix processor was designed for medical implants but could also be used for ultralong-lived environmental monitors and military surveillance, the scientists said at the IEEE Symposium on VLSI Circuits in Honolulu.
"Our chip and battery together are about 1,000 times smaller than the technologies being used for implants today," said David Blaauw, an electrical-engineering professor at the University of Michigan. Blaauw performed the work with fellow EE professor Dennis Sylvester and doctoral candidates Scott Hanson and Mingoo Seok.
If the Phoenix were powered by an ordinary watch battery, it would last for 263 years while in sleep mode. The chip, however, was designed to meet the requirements of an implant to monitor the pressure inside an eyeball. That restricted its size to less than a cubic millimeter, including its thin-film battery.
Nevertheless, since the device consumes just 30 picowatts during sleep modeand because it needs to take a measurement only occasionallythe expected lifetime of the implanted chip and integrated battery is longer than three years.
"Our processor was designed from the ground up to be low power," said Sylvester. "We believe we are the first group to make low sleep-mode power our No. 1 concern."
Besides long-lived medical implants, the Michigan researchers envision the Phoenix's use in other settings. The military could sprinkle self-powered sensor chips onto the battlefield, environmental scientists could disperse them in the air or water to detect pollution, and construction crews could mix them into concrete for monitoring the structural integrity of buildings and bridges, the group suggested.
Sleep mode dominates many sensing applications, since the chips need to awaken only occasionally to briefly make a measurement, wirelessly send off their results and then go back to sleep. In many such applications, the sensors will spend more than 99 percent of their time asleep.
Consequently, in the Phoenix design, sleep is the chip's "normal" mode. The device awakens every 10 minutes for a tenth of a second to measure and transmit. Then it goes back to sleep.
To reduce the overall consumption, the researchers used tried-and-true 180-nanometer design ruleswhich have less leakage overalland reduced the chip's power supply voltage to 0.5 V rather that the normal 1 to 1.2 V.
However, the biggest innovation responsible for the ultralow power consumption claimed by the researchers was the redesign of the Phoenix's power gates. "Power gates supply power from the battery when a chip is awake and block current from parts of a chip not essential for memory during sleep mode," said Blaauw.
The typical power gate uses a wide channel so that it can quickly power up a sleeping chip. But the Phoenix trades off speed for lower consumption by using a very narrow channel for its power gate transistors. By narrowing the channel, the team reduced leakage current to just 30 picoamps.
Next, the researchers plan to integrate a transmitter and antenna onto the chip, so that it can take measurements and wirelessly transmit its results.