For a related how-to article, see Timing-driven Simulink FPGA synthesis.
San Jose, CA—Altera Corporation's DSP Builder 8.0, the first tool to generate timing-optimized RTL code from Simulink designs. While Altera and its competitors have offered DSP synthesis tools for several years, DSP Builder 8.0 offers several unique features that boost performance. Specifically, DSP Builder 8.0 automatically adds pipelined stages and registers to meet user-specified clock rates, and implements time division multiplexing to share resources such as multipliers. DSP Builder 8.0 also supports design scaling, allowing designers to quickly change the number of channels processed by filters and other blocks.
DSP Builder 8.0 targets functions such as digital upconversion (DUC), downcoversion (DDC), crest factor reduction (CFR) and digital predistortion (DPD). DSP Builder version 8.0 includes design examples for multi-antenna, multi-carrier WiMAX and WCDMA DUC and DDC designs.
DSP Builder 8.0 is available now. For more information, see www.altera.com/pr/dsp.