"Systems-on-chip put logic alongside memory on the same chip, but have had to compromise on performance since both were fabricated with the same process. By putting the memory devices on top of the logic devices, using separately optimized processes, BeSang is increasing density without compromising performance."
BeSang's process works by first fabricating the logic on one wafer with normal vias and interconnection layers. Then memory devices are fabricated separately on a donor wafer, and the two wafers are aligned and bonded to form a single 3-D unit.
Because logic and memory are processed on different wafers, both can use normal 850-degree C processes that have been separately optimized. The two wafers are then sent to another line, where they are precisely aligned and bonded using a proprietary low-temperature, 400-degree C process.
The donor wafer essentially contains one vertically oriented bit cell, which, after bonding, is etched into millions of pillar-shaped transistors that control individual bit cells. The final step interconnects the individual bit cells and caps the 3-D wafer with final metallization layers.
"The cost of BeSang's 3-D chips should be much lower, because you are reducing the overall chip area by putting all your logic in one process on the bottom wafer, putting all of your memory, using a different process, on the top wafer, and using the conventional vias to interconnect them," Sze predicted.
Demonstration chips were processed on 8-inch wafers using 180-nanometer CMOS technologies. The test chip contains 128 million vertical transistors suitable for fabricating flash, DRAM or SRAM memory cells atop logic circuits. The bottom layer of logic was separated from the upper memory layer by single-crystal silicon, and two metal interconnection layers containing the vias between logic and memory. The top memory layer was lifted from the memory donor wafer, which contained alternating layers of n- and p-type semiconductors. The donor wafer was reused four times, each time allowing one big vertical n-p-n transistor to be deposited atop the logic wafer.
After etching individual vertical transistors for bit cells, an additional metal interconnection layer capped the 3-D wafer before dicing.