Mountain View, Calif.Synopsys Inc. announced the availability of a full range of silicon-proven DesignWare DDR IP solutions for SoCs that require an interface to high-performance DDR3, DDR2 and DDR memory subsystems.
The DesignWare DDR IP solutions deliver memory system performance of up to 1600-Mbit/s, the maximum data-rate of the JEDEC DDR3 specification.
The solutions include configurable protocol and memory controllers, integrated mixed-signal PHYs including I/Os and verification IP. The DesignWare DDR IP portfolio provides designers with scalable solutions that help reduce risk and speed time-to-market for applications such as digital home, digital office, data center and storage.
The comprehensive DesignWare DDR IP portfolio consists of three product lines, including DDR3/2, DDR2/3-Lite and DDR2/DDR, all of which have been validated and fully characterized in Synopsys' silicon test chips and support two generations of DDR SDRAM.
The DDR3/2 IP helps satisfy the needs of the highest performance interfaces with operation at up to 1600-Mbit/s and offers a wide range of in-system calibration capabilities to ease implementation of the interface at higher data rates.
The DDR2/3-Lite IP is an area- and feature-optimized IP solution operating at up to 1066-Mbit/s using DDR2 or DDR3 SDRAMs. The DDR2/3-Lite IP is intended for SoCs that initially target DDR2 SDRAMs, and has the option of migrating to DDR3 when it becomes more cost effective without the need to modify the current SoC design.
The DDR2/DDR IP operates at speeds up to 1066-Mbit/s and is available in leading 130nm, 90nm and 65nm process technologies.
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