The folks at Lattice Semiconductor have announced the immediate availability of their ispLEVER Classic version 1.2 design tool suite.
This tool suite supports all Lattice SPLD, CPLD and select FPGA families. In particular, Lattice's ispLEVER Classic tools now provide full production support for the recently released ultra-low-power ispMACH 4000ZE CPLD family and also include user-friendly support for several innovative new silicon functions.
ispLEVER Classic 1.2 also includes the newest versions of Synopsys' Synplify synthesis and Aldec's Active-HDL simulator EDA tools.
Pricing and availability
Lattice's ispLEVER Classic 1.2 for Windows is available now for download from the Lattice website (www.latticesemi.com) without charge. UNIX and Linux versions are available with the full ispLEVER software tool suite. The full ispLEVER design tool suite for Windows is priced beginning at $895.
About ispMACH 4000ZE CPLDs
The ultra low power ispMACH 4000ZE family ranges in density from 32 to 256 macrocells, with new system integration capabilities including an on-chip oscillator and timer, input hysteresis and Lattice's new Power Guard feature.
Power Guard lowers power consumption by selectively disabling unused input pins so that they do not switch and needlessly consume dynamic power. The on-board oscillator is useful for housekeeping tasks such as "heartbeat" functions, digital de-glitch, and control state machines. "Always on" input hysteresis is provided for each pin.