Venice, Florida — Calypto Design Systems Inc. has added new sequential power optimizations and support for VHDL designs to PowerPro CG (clock gating an automated register transfer level (RTL) power optimization solution.
Support for VHDL in PowerPro CG extends the benefit of power savings to more designers, in particular those in European consumer and wireless electronics companies where VHDL is the dominant design language. PowerPro CG automatically reduces power by reading a synthesizable RTL design captured in VHDL or Verilog and generating a RTL design identical to the original design with additional clock-gating enable logic. The latest version of PowerPro CG is shipping now. It runs on Linux and is a no-cost upgrade for existing customers.
PowerPro CG identifies sequential clock-gating enable conditions based on Calypto's patented Sequential Analysis Technology. The new sequential optimizations added to PowerPro CG save additional power in heavily clock-gated RTL code, such as existing consumer and wireless designs that previously have been optimized manually. The latest release of PowerPro CG finds clock-gating enable conditions beyond those already present in the design. The output of PowerPro CG is comprehensively verified with sequential equivalence checking to ensure no functional changes are introduced.
The latest PowerPro CG release includes leading-edge graphical display and navigation features in the PowerPro Analyzer. These capabilities allow designers to thoroughly understand the sequential nature of the power optimizations added to their RTL code by PowerPro CG.
For more details, contact Calypto at email@example.com.