The folks at EMA Design Automation, a full-service provider of Electronic Design Automation (EDA) solutions, have announced that their TimingDesigner version 9.1 includes support for SDC, which provides the ability to interface with FPGA and ASIC design flows.
They also say that TimingDesigner is the industry standard tool for interface timing design and that it provides an easy to use and intuitive method for defining and analyzing interface timing requirements. Furthermore, they claim that the introduction of version 9.1 makes TimingDesigner the only tool that can generate SDC timing constraints from a timing diagram. This enables users to visually define design requirements and then automatically generate SDC to drive place and route.
Generating SDC directly from a timing diagram removes any confusion as to the intent behind the constraints and allows users to visually debug and refine their SDC with ease. It also greatly reduces the learning curve for users new to the SDC format.
The initial release of TimingDesigner with SDC support focuses on the Altera FPGA design flow.
TimingDesigner 9.1 also includes a number of general productivity enhancements and updates as part of the ongoing efforts to provide the highest quality timing analysis software on the market.
Availability and pricing
TimingDesigner 9.1 will be available at the end of October 2008 starting at $2,995 and is free to existing customers with a valid maintenance contract. For more information, visit www.TimingDesigner.com or call 800-813-7494.