The folks at Lattice Semiconductor have announced that their LatticeSCM FPGA family-based SPI4.2 MACO ("Masked Array for Cost Optimization") cores have been enhanced by adding sophisticated link-layer buffer management options.
They claim that, compared to competitive FPGAs, the LatticeSCM FPGA family has offered the industry's most feature-rich SPI4.2-based cores and bridge reference designs at the lowest cost, power, and printed circuit board footprint. They also say that these new features enhance this solution portfolio by allowing designers the option to use a parameterizable buffer manager for applications needing per-channel bandwidth management.
The LatticeSCM FPGA platform provides designers with multiple hardened SPI4.2 cores using Lattice's exclusive MACO structured ASIC technology. MACO technology delivers pre-engineered, standard-compliant IP functions, developed by Lattice, that shorten end-system time to market and dramatically lower device cost, power and PCB footprint targets. These new features provide designers with a programmable buffer manager capable of:
- Up to 16 separate physical FIFOs per TX/RX direction
- Packet over-flow and error drop
- Both store and forward as well as cut-through operation
- Parameterizable buffer depth and thresholds
- Dynamic channel provisioning
- Programmable sequencer-based scheduler
Click Here for further information on these cores and/or Click Here to find an XAUI-to-SPI4.2 bridge solution.