LONDON FPGA vendor Xilinx Inc. (San Jose, Calif.) has announced the availability of a "digital front-end" or DFE for 3rd Generation Partnership Protocol (3GPP) Long Term Evolution (LTE) wireless communications systems.
The design files, application note and integration instructions can be downloaded free of charge, Xilinx said, but there is the catch that downloaders must be "registered" as Xilinx customers. So it seems you get the design files for free but you have to buy a lot Virtex-5 FPGAs. The download website is www.xilinx.com/esp/wireless.htm#rf
Xilinx said the LTE DFE platform consists of logic for digital up-conversion (DUC), digital down conversion (DDC) and crest factor reduction (CFR) that together form a complete LTE radio subsystem.
However, there is some confusion here because a complete LTE radio subsystem would have to include radio frequency circuits, which Xilinx does not appear to be offering.
The so-called DFE is compatible with a digital pre-distortion (DPD) circuit design already available from Xilinx, the company said. Xilinx claimed that use of its circuits in FPGA offers a quicker time to market than application-specific standard part (ASSP) and application-specific integrated circuit (ASIC) design methods. The company added that there not yet any ASSPs or ASICs available for LTE systems.
The LTE DFE design is configurable and has been architected to support seven single and multi-carrier implementations, including: single carrier 5-, 10-, 15-, and 20-MHz bandwidths; dual carrier 5- and 10-MHz bandwidths; and four-carrier 5-MHz bandwidth. Using the DSP tool suite offered by Xilinx, the design can be customized to meet the needs of company-specific 3GPP-LTE radio applications, the company said.
"LTE is set to be the dominant wireless standard over the coming years, and developers need to ensure that they have products available for operator trials within a small window of opportunity, and this window is rapidly closing," said David Hawke, senior product manager of radio and wireless interfaces for Xilinx, in a statement.
Xilinx said that 60 percent of the overall capital expenditure of a basestation is within the radio, which is also responsible for much of the operational expenditure incurred during the lifetime of the product.
The 3GPP LTE reference design is delivered with an application note and design files for Virtex-5 device architectures, test vectors and scripts that allow designers to evaluate performance in Matlab environment. Instructions for integrating the reference design into the target system design are also included.