Venice, Florida — Mentor Graphics Corp. announced the availability of an open-source SystemVerilog solution for users adopting the Open Verification Methodology (OVM). The solution enables the easy and flexible reuse of legacy Verification Methodology Manual (VMM) code within an OVM environment.
VMM-based verification components can now be seamlessly reused within an OVM environment. In addition, entire VMM environments can be reused without modification within an OVM environment through the use of a new OVM/VMM Interoperability library that provides the data and semantic conversions between the old and new environments. VMM sequential stimulus can be reused as well, and integrated with OVM's sequences thus preserving and enhancing existing stimulus generation capabilities.
As an active member of the Accellera VIP Technical Subcommittee (TSC), Mentor has worked with other committee members to define the requirements for interoperability among different verification methodologies. Mentor's solution conforms to the Accellera VIP-TSC's set of requirements for SystemVerilog base class library interoperability that was approved by a technical subcommittee vote on December 3, 2008.
"Interoperability of verification IP (VIP) is critical to achieve productivity gains as design teams reuse legacy IP in an OVM environment," said Stephen Bailey, Director of Marketing for the functional verification division at Mentor Graphics. "This solution provides an optimal means for VMM users to adopt the OVM with minimal effort. It also paves the way for the TSC to deliver an interoperability guideline document."
The Mentor open-source SystemVerilog source code and documentation is distributed under the Apache2.0 open-source license, and is available immediately in the "Community Contributions" area of the OVM World site at OVMworld and at the Mentor Graphics functional verification website at Mentor Cookbook.