The folks at Synfora – who specialize in algorithmic synthesis tools used to design SoCs and FPGAs – have announced new versions of their PICO Extreme and PICO Extreme FPGA algorithmic synthesis design tools that will achieve higher performance and smaller area than the previous generation of the tools.
PICO Extreme is an advanced optimizing compiler that transforms a sequential, untimed C algorithm into highly efficient RTL (Register Transfer Language), reducing design and verification time, allowing designers to find the lowest cost implementation and enabling very rapid reaction to changes in the design specification. Enhancements announced today enable designers to create and analyze hardware designs more effectively, and include QoR (Quality of Results) improvements in terms of area, throughput, timing and timing correlation, as well as user feedback improvements.
In the new version of PICO Extreme, significant advances in scheduling algorithms enable the compiler to optimize registers in a design. In a suite of 50 actual customer designs, this yielded area improvements in the range of from 5 percent to 20 percent, with a corresponding reduction in silicon cost. Sophisticated analysis of variable loop bounds, combined with an innovative new approach to handling early exits from loops, are said to provide performance improvements in the 10 percent-to-30 percent range on complex designs.
Achieving high productivity on complex designs requires that synthesis tools provide the user with sophisticated analysis, feedback, and debugging capabilities to understand the performance and area bottlenecks in the design. The enhancements to PICO Extreme 08.03, including those to the reporting and feedback capabilities, improve the ability to analyze throughput bottlenecks, provide greater visualization and reporting of the hardware cost, and allow automatic detection and feedback on potential deadlock scenarios.
Using a recursive system composition methodology, PICO Extreme transforms a sequential, untimed C algorithm into highly efficient RTL. It allows use of familiar design styles, reduces runtime and achieves unprecedented quality of results that compete with hand design. Recursive system composition is enabled by Synfora's innovative TCAB (tightly coupled accelerator block) technology, allowing users to designate parts of their algorithms as application-specific building blocks, which are C procedures that can be designed and verified standalone. The PICO Extreme compiler automatically integrates and schedules these blocks as if they were primitive computing elements.
PICO Extreme is in use at a growing number of leading companies for next-generation SoCs and FPGAs in video, wireless, imaging and security applications. It has been shown to achieve 30 percent more design functionality, differentiation and power efficiency with 30 percent less verification time, design resource commitment and silicon cost.
Synfora is demonstrating the enhanced PICO Extreme design tools at the Electronic Design and Solution Fair 2009 (EDSFair2009) in Yokohama, Japan, January 22 – 23 (Booth 112).