The folks at Lattice Semiconductor have announced the availability of a low cost programmable PCI Express-to-High Speed Serial (HSS) bridge for the CAP12-120, a Small Office Home Office (SOHO) Voice Over IP (VOIP) platform running on Intel architecture. This bridge design has been implemented in the LatticeECP2M FPGA. The solution utilizes the LatticeECP2M's low power, high-performance SERDES, and a Lattice PCI Express Intellectual Property (IP) core.
The Lattice FPGA solution is used in the Intel CAP12-120 reference design, based on the Intel Celeron M 915GM processor and chipset. To address the voice, video and data communications needs of small and medium businesses and enterprises (SMB/SMEs), Intel has added two versatile yet affordable Multi System Business Gateway reference designs to its family of converged solutions platforms.
Announced at VoiceCon 2008, the Intel CAP12-120 is a proof-of-concept design for software-based IP-PBX/MSBG solutions that enables developers to build a converged communications device for up to 120 seats quickly and cost effectively. These all-in-one-box solutions are capable of delivering a variety of services and can be scaled and modified easily in software to meet the requirements of different customer premises. The fully integrated platforms include all the necessary hardware and software components for building cost effective IP-PBX/MSG solutions, reducing the time, effort and development cost of these platforms.
The LatticeECP2M family provides an ideal FPGA platform for implementation of high performance serial protocols such as PCI Express and Gigabit Ethernet. The Lattice PCI Express IP, combined with Lattice's own high-speed SERDES and the economical, low power, high-performance LatticeECP2M fabric, provides designers a powerful platform for satisfying their high-performance bridging and co-processing needs. The flexibility of the LatticeECP2M fabric provides designers with a platform to develop a variety of applications while still meeting very aggressive cost targets.
About the LatticeECP2M FPGA family
The low-power LatticeECP2M FPGA family provides performance-enhancing features that are typically available only on more expensive high-end FPGAs. The LatticeECP2M family supports logic densities from 20K LUTs up to 100K LUTs, has high performance DSP blocks, supports DDR2 memory interfaces at 533Mbps and up to 840Mbps generic LVDS performance.
Some of the high-end features incorporated into the LatticeECP2M family include embedded SERDES I/O and the most on-chip memory in its class. The LatticeECP2M family supports up to 16 channels of embedded SERDES, operating up to 3.125Gbps. The SERDES supports protocols such as PCI Express, Ethernet (1GbE and SGMII), CPRI/OBSAI, SMPTE and JESD204. In addition to embedded SERDES channels, the LatticeECP2M FPGA family offers Embedded Block RAM capacity ranging from 1.2 Mbits to 5.3 Mbits.