Synfora has announced Pico Extreme Power, an synthesis tool to automatically minimize power consumption at the system level based on a variety of techniques, including automatic multi-level clock gating insertion.
Multi-level clock gating enables clock gating to be applied to a computation block in an application accelerator at any level in the hierarchy.
Synfora said that Pico Extreme Power has delivered savings of up to 50 percent using this technique.
Researchers at Rice University were amongst the first users of Pico Extreme Power and designed and evaluated a low-density parity check (LDPC) decoder for the next generation wireless handset SoC. They demonstrated a 23.5 percent reduction in dynamic power over an identical design using a standard flow, according to Synfora.
Similarly, the Indian Institute of Science (IISc) evaluated the effectiveness of the approach using eight complex applications from video, imaging and wireless domains.
Synfora said the results indicate as much as 50 perent savings in dynamic power for executing a single task in some of the applications and as much as 30 percent savings while executing a large number of tasks. The average power reduction over all applications was 22 percent for a single task and 15 percent over multiple tasks, said Synfora.
In two additional designs generated using Pico Extreme Power, RTL level power estimates done with the Atrenta SpyGlass-Power solution, showed power reductions of 16 percent and 53 percent compared with designs without block-level clock gating, said Synfora.
Synfora serves global customers in the audio, video, imaging, wireless, and security segments of the IC design market.