Commack, NY Tensilica Inc. today announces the ConnX family of DSPs that it is positioning as the best solution yet to meet the performance and cost requirements of 3G and 4G system-on-chip designs.
Leading the family out of the gate is the ConnX Baseband Engine for wireless infrastructure, featuring an optimized instruction set with 200 new instructions, a high memory bandwidth of 256 bytes per cycle, scalable clustering, and efficient compiler support with an easy programming model for SIMD vectorization and other DSP functions.
Essentially comprising configurations of Tensilica's Xtensa LX customizable processor cores for SOC (system-on-chip) designs, the new family embodies a belief within Tensilica that dataplane processing units (DPUs), which combine both DSP and RISC characteristics, can deliver 10x to 100x the performance of either DSP or CPUwith better flexibility and verification than RTL.
According to Will Strauss, president of Forward Concepts, Tensilica has done well morphing its basic Xtensa RISC architecture into a compelling DSP engine. So much so, that, "Tensilica is seeing that its processor is shipping more as a DSP instead of a RISC, with 350 million cores for DSP on cellphones for audio processing."
However, combining DSP with RISC is not new: Texas Instruments led the way with its highly successful OMAP architecture, followed by Analog Devices with the Blackfin. So what's the differentiator?
According to Chris Rowen, chief technology officer at Tensilica, "OMAP and Blackfin represent one specific compromise between CPU and DSP, but what Xtensa represents is a continuum [of optimization]." This continuum, brought about by the configurability of the Xtensa instruction set, "means you can optimize fully for your application," he said.
At face value, the ConnX announcement can be viewed as a rebranding exercise: The ConnX Baseband Engine joins the proven quad-MAC Vectra LX DSP option, which is now re-branded as the ConnX Vectra Engine. The ConnX Vectra Engine has been used in many customer designs and is an integral part of the re-branded ConnX 545CK standard DSP. The ConnX 545CK was previously known as the Diamond 545CK, which received a BDTIsimMark2000 score of 3820, the highest of all licensable cores evaluated by BDTI.
"Our customers have been customizing Xtensa LX processors for complex DSP functions in the SOC dataplane for years now," stated Jack Guedj, Tensilica's president and CEO, in a corporate release. "The majority of our over 350 million cores shipped have performed complex DSP functions. Now, with these pre-designed ConnX DSP modules, our customers will be able to get new next-generation products to market much faster."
However the Baseband Engine brings a lot more to the ConnX party than simple relabeling. Instead, the company made quite a few enhancements that make it very suited to 3G/4G basestations and multimode, multi-standard terminals.
To get a summary of the requirements of these standards, along with a detailed overview of the ConnX Baseband Engine and how it can be applied, see The ConnX Baseband Engine and its application in LTE with MIMO.
Block diagram of ConnX Baseband Engine with key features including 200 new instructions, 8-way SIMD, 3-way VLIW architecture with 16 18bx18b MACs/cycle and two 160-bit vector register files (20 bitsx8, 40bx4 vector types)
Highlights of the Baseband Engine's suite of enhancements include 200 additional instructions to handle such OFDM functions as finite input response filters, fast Fourier transforms, FFT and matrix manipulations. Also worth noting is an enhanced memory structure for higher bandwidth and thoughput, automatic vectorization for ANSI C programs and an eight-way SIMD, three-slot VLIW (very long instruction word) architecture with up to two load/stores plus one MAC and one ALU operation per cycle.