SAN FRANCISCOEDA vendor Mentor Graphics Corp. Monday (June 29) announced extensions to its Catapult C Synthesis tool to support full-chip high-level synthesis (HLS), upgrades billed by company executives as the most significant enhancements to Catapult C since the tool was introduced in 2004.
Extensions to the tool enable it to support control logic and manage low power design requirements, Mentor said. The result is that designers are able to use pure ANSI C++ for both algorithmic blocks and control logic blocks, the company said.
"This really enables us to be able to do what customers want us to dosupport full-chip synthesis," said Simon Bloch, vice president and general manager of Mentor's ESL and HDL design and synthesis division. "This is really significant for us."
Mentor and others say designers are turning to HSL, or electronic-system level (ESL) design, in order to cope with the rising complexity of designs. By automating RTL implementation from C++ specifications, proponents say, HSL helps designers accelerate time to RTL and reduce effort spent on verification, currently one of the biggest bottlenecks in leading-edge chip design.
But while HSL and ESL have been hyped for years, uptake remains limited. This has lead to a perception among many that the transition from RTL to ESL design is taking longer than expected.
But Bloch said that while ESL marketing efforts may have been initiated too early, the transition itself is occurring in much the same way as the transition from gate-level design to RTL did.
"When I looked into the evolution of ESL versus RTL, I don't think the evolution of tech is taking longer time than RTL did," Bloch said.
Mentor executives offered results from a third-party survey of more than 800 chip designers that listed faster verification/fewer bugs as the top reason for using high-level synthesis. This reason was cited by 68 percent of respondents, while 64 percent cited faster time to RTL (respondents were asked to provide two answers).
According to Shawn McCloud, Mentor's high-level synthesis product line director, the fact that verification was cited as the top reason for using high-level synthesis might surprise some people.
"People have always thought HLS would give them faster time to RTL," McCloud said. "But the survey shows that users really view HLS as helping them solve the verification challenge. This is really a primary motivation to adopt HLS."