Calypto Design Systems will be demoing at DAC 2009 its PowerPro MG tool that automatically generates power-optimized RTL by taking advantage of the low-power modes available in today's leading on-chip memories.
The tool's "memory gating" technique eliminates costly and time-consuming manual coding.
PowerPro MG (Memory Gating) works together with the company's PowerPro CG (Clock Gating) tool, which reduces power by implementing sequential clock gating logic in the non-memory portions of an RTL design.
"To achieve the lowest power implementations in today's complex SoCs, both static and dynamic power of logic and memory must be addressed. The flow must include multi-cycle sequential analysis for optimization and verification," said Gary Delp, VP and technical director of the Spirit Consortium and Co-Chair of the IEEE1801, Standard for Design and Verification of Low Power Integrated Circuits Committee. "Calypto's PowerPro family delivers an extremely effective and unique solution to SoC design teams."
"With PowerPro MG, designers can, for the first time, apply sequential analysis techniques to automatically generate memory gating logic that significantly reduces both static and dynamic on-chip memory power," said Tom Sandoval, chief executive officer of Calypto Design Systems.
Currently, the design of logic used to control low-power memory modes requires hand-coding that is time-consuming and error-prone. By automatically generating logic to control low-power modes, PowerPro MG enables the lowest-power SoC possible and reduces that portion of the design cycle from weeks to hours.
Using Calypto's patented sequential analysis technology, the tool constructs new memory gating logic that works in conjunction with the low-power memory modes to optimize for the lowest possible power memory implementation.
According to Sandoval, PowerPro MG fits seamlessly into today's RTL synthesis flows. The tool reads in an RTL design written in VHDL or Verilog as well as the applicable memory models. PowerPro MG then generates new power-optimized RTL that looks identical to the original RTL except for the addition of the new memory gating logic.
Calypto worked with Virage Logic, a leading embedded memory IP provider, to maximize the opportunity for memory power savings.
"Using PowerPro MG in conjunction with Virage Logic's SiWare Memory products will help enable our customers to deliver designs that are as power-efficient as possible," said Brani Buric, executive vice president, marketing and sales, of Virage Logic.
Calypto's PowerPro MG runs on PC platforms running Linux and is priced at $295,000 for a one-year time-based license.