LONDON Renesas has started using new tools that the company says can halve system-in-package (SiP) design time since they rely on a top-down (predictive) design approach in which key characteristics, such as design quality and heat dispersion, are verified during the initial design stage.
The company plans to develop a range of SoC devices, MCUs, and memories in a single package, using what it terms the "SiP Top Down Design " environment that replaces the conventional back annotation (analytical) design methodology, in which these characteristics are analyzed at a late stage of the SiP design process.
Renesas says with existing SiP design methods, the analysis of electrical and thermal characteristics is independent of the wire bonding design and package substrate wiring design processes. As a result, it is necessary to update the substrate data manually for each tool used in chip and wiring analysis.
Its latest "design environment" uses an integrated design database to provide unified management of design data and easy connections for analysis of electrical or heat dissipation characteristics.
Data on chip shapes and positions as well as chip-to-chip connection data can thus be extracted from the database and connected to the substrate layout tool. In turn, wire bonding and substrate pattern data from the substrate layout tool can be connected to other analysis tools.
A common interface is provided for running the tools and making settings.
The revised design environment includes an electromagnetic field analysis tool that supports large-scale substrates.
This means it is not necessary to divide up the area to be analyzed. In addition, simulation condition setting and result determination for circuit simulations are automated. It is therefore possible to estimate noise at the initial design stage based on the electrical characteristics.
Another advantage, according to Renesas, is that the design methodology now extracts from the substrate layout data information on the conductor pattern area share (remaining copper ratio), layer thickness, and materials of the internal SiP package wiring, power plane, etc., the number of via holes between layers, and the shapes and positions of the chips, and it automatically builds an environment for the heat dispersion evaluation package model.
Another novel function is said to apply the power consumption distribution of the SoC to the thermal analysis model so that the distribution of heat generation within the chips is taken into account.
These increase the accuracy of the models and speed up thermal analysis.
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