GATeIC's SoftGATe spec-to-GDSII automation platform, optimized for Synopsys' Galaxy Implementation
Platform, enables ASIC designers to automate the creation and optimization of implementation-ready custom IP for ASICs within days of settling on specifications.
Designing a single instance of a digital signal processing chain comprised of digital blocks can consume months of engineering resources and time.
SoftGATe generates bit-accurate implementations for a given set of specifications, configures the corresponding HDL code, and implements all designs using Synopsys Design Compiler synthesis on the Galaxy Platform.
SoftGATe generates input for Synopsys' IC Compiler physical implementation tool, the Star-RCXT parasitic extraction tool and the PrimeTime PX power analysis solution to generate fully placed, routed GDSII, and extracted power for IP exploration and trade-off
According to the company, running all bit-accurate designs through the Galaxy Platform in parallel minimizes time-to-optimized-design, by creating implementations that strike the desired balance between area, power, performance and other specs, to optimize manufacturing cost per unit of power
The company said that SoftGATe was used recently on a 5th generation mixed-signal IC, where the platform churned through 5.8 million combinations to arrive at a final design that reduced power by a minimum of 35 percent while reducing area by more than 10 percent, as compared to the previous IC design.
"In some cases, SoftGATe enables the implementation of a very complex signal processing block that engineers considered to be impossible in a particular target," said Gary Mekikian, CEO of GATeIC.
According to Steve Smith, senior director of platform marketing at Synopsys, "GATeIC's approach to automating the high-level implementation of custom DSP building blocks for ASICs using the Galaxy Implementation Platform helps designers reduce overall costs while increasing productivity and minimizing schedule risk."
Since SoftGATe can customize and generate digital signal processing blocks with limited human intervention, fully implemented and tested blocks can be made available to ASIC makers for evaluation within days of receiving specs.
GATeIC was founded in 2006 with a mission to harness the power of advanced optimization algorithms to identify optimal digital signal
processing blocks for a given set of specs.