Arasan Chip Systems, Inc. has released its MIPI (Mobile Industry Processor Interface) High Speed Synchronous Interface (HSI) controller IP and software stack.
The MIPI Alliance was formed drive consistency in processor and peripheral interfaces, promoting reuse and compatibility in mobile devices.
The High Speed Synchronous Interface is a full- duplex, low latency protocol, that is optimized for die-level interconnect between an application processor and a baseband chipset.
The HSI controller IP and software stack are compliant with the HSI v1.0 specification. The IP core is compliant with the HSI Physical Layer Draft v1.1.
By integrating this standard interface, application processors and wireless chipset developers are assured of an ecosystem of inter-operable components which can be combined to develop region and application-specific mobile platforms, according to Arasan.
The HSI physical interface consists of two sets of unidirectional data and control signals combined to form a full-duplex connection. The protocol accommodates up to eight logical channels over this interface with an aggregate bandwidth of 200 Mb/s in each direction.
Optimized for deployment in mobile platforms, the protocol incorporates features to reduce power through clock gearing and dynamic frequency scaling.
The layered HSI software stack is architected to be easily portable to multiple OSes and hardware platforms. The stack can also be used on SoCs that have multiple HSI interfaces. The stack supports multiple priority levels per logical channel and DMA modes for efficient data transfer.