Analog Devices, Inc., has expanded its low-power data converter portfolio with 26 analogue-to-digital converters, ADCs, for effective high-performance, power-efficient communications, portable device, instrumentation and healthcare applications.
The company is claiming three data converter technology industry firsts for 16-bit ADCs:
- ADI's AD9269, the industry's first 16-bit 80MSPS low-power, dual ADC with quadrature-error correction (QEC)
- ADI's AD9265, the industry's first single-channel, 16-bit low-power ADC spanning 80 to 125 MSPS (megasamples per second)
- ADI's AD9266, the industry's smallest single-channel 16-bit low-power ADC spanning 20 to 80 MSPS.
The new ADC products provide designers a flexible, future-proof platform to differentiate their systems without changing the core design by migrating either resolution or bandwidth support by means of space efficient pin compatible families. In addition, the new ADCs' energy efficiencies provide power consumption improvements without impacting system-level performance.
In addition to the AD9269, AD9265 and AD9266 flagship converters and their various speed grades, ADI has also introduced 23 single-channel low-power ADCs, bringing the number of low power data converters ADI has brought to market in the last 180 days to 44. The power consumption savings across these ADCs claim to be as high as 87 percent compared to equivalent competitive offerings operating comparable ADC functions.
The dual-channel AD9269 16-bit low-power ADC consumes 93 mW per channel, which is 6.5 times lower than competing devices. The AD9269 is a monolithic, dual-channel 16-bit, 20/40/65/80 MSPS ADC, featuring a high performance sample-and-hold circuit and on-chip voltage reference. The device is also the industry's first 16-bit ADC family to include a QEC and DC offset digital processing block. The blocks dynamically minimize the errors produced in an in-phase/quadrature (I/Q) complex signal receiver system. By using the QEC block, system designers can relax component matching requirements by reducing gain and phase errors due to component mismatches. The net result can also enable a more robust receiver design. In addition, the DC-offset algorithm minimizes offsets commonly found in DC-coupled applications. The product uses multistage differential pipeline architecture with output error correction logic to provide 16-bit accuracy at 80-MSPS data rates and guarantees no missing codes over the full operating temperature range. The ADC operates from a 1.8-V supply and contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital-test-pattern generation. Samples are available now with production quantities available in January, 2010.
The single-channel AD9265 low-power, 16-bit ADC was designed to support communications applications requiring low bill-of-material costs, small size, and flexibility. Consuming only 370 mW, this breakthrough in power consumption represents a 51 percent savings compared to competitive low-power solutions. The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The AD9265 features a wide bandwidth differential sample-and-hold analogue input amplifier supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabiliser provides means to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The ADC output data are either parallel 1.8 V CMOS or 1.8 V LVDS (DDR). Flexible power-down options allow significant power savings, when desired. Programming for setup and control are accomplished using a 3-bit SPI-compatible serial interface. Production quantities are available now.
The single-channel AD9266 16-bit, low-power ADC is available in a small 5 mm x 5 mm package, and the pin-out supports resolutions from 10 to 16 bits. The low-power, multistage ADC core is based on a proprietary, high-performance, sample-and-hold circuit and on-chip voltage reference. The product uses a differential-pipeline architecture with output-error-correction logic to provide 16-bit accuracy at 80 MSPS data rates and guarantees no missing codes over the full operating temperature range. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the SPI. A differential clock input controls all internal conversion cycles. An optional DCS compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data are presented in offset binary, Gray code, or twos complement formats at double-data-rate low-voltage CMOS levels. A data output clock (DCO) is provided to ensure proper latch timing with receiving logic. Samples are available now with production quantities available in January, 2010.