PARIS Arteris Inc. (San Jose, Calif.), a supplier of networking-on-chip intellectual property, has introduced two on-chip interconnect products to address interconnect issues facing IC designers, including the design of ICs with lower power, higher performance and lower silicon area.
Arteris traditionally targets high-end very complex designs (multiple, multiple IPs, high performance, complex power management. With the FlexNoC and FlexWay packages, Arteris said it has broadened its scope to a larger set of designers "with a scaled back solution which works within existing bus-based designs."
Arteris specified that FlexNoC is for implementing NoCs in medium to high-end SoC designs and FlexWay addresses the needs of less complex SoC designs.
Arteris said FlexNoC provides users with the choice, per connection, to use a standard packet format or a zero latency packet format to carry protocol information. The use of the zero latency packet format allows users to eliminate any penalty involved in the packetization process.
Among other applications, Arteris noted IC subsystems, such as video, graphic subsystems, as well as medium complexity SoCs.
The FlexWay product, the company noted, can be used as a bus replacement for simple SoC designs but also to address peripheral interconnect applications on more complex designs. Its applications are advanced high-performance buses (AHB), OCP busses, multi-layered AHB, and peripheral interconnect.
Arteris said its FlexNoC and FlexWay products are supported by the unified FlexArtist design tool set that assembles NoC IP to accelerate SoC delivery. The FlexArtist design environment is indeed claimed to allow users to output RTL and SystemC models to provide an interconnect model for every stage of the SoC design flow.