PARIS EDA and IP company Dolphin Integration SA (Meylan, France) said it has enhanced its Cassiopeia architecture for single via programmable Read-only memory (ROM) with a capability to operate from nominal voltage down to 1.1 V in the TSMC 130 nm low power process.
Dolphin Integration said it has developed the Cassiopeia architecture for ROM to address the requirements of low power SoCs, especially for portable applications. Cassiopeia, the company claimed, records low power consumption at nominal voltage on applications such as RFID or high-end mobile.
Dolphin Integration specified that, with its "Two in One" patent, Cassiopeia is up to 20 percent denser than contenders, which enables SoC designers to reduce manufacturing costs.
Cassiopeia is in mass production in the TSMC 130-nm process and, Dolphin Integration said it is possible to migrate to other foundries, starting with SMIC.