Winchester, UK - Lattice Semiconductor Corporation and Praesum Communications have announced the availability of the Serial RapidIO 2.1 endpoint soft IP core for the LatticeECP3 FPGA family, which supports 1x, 2x and 4x lane configurations at up to 3.125 Gbps lane speeds, and claims to offer the lowest cost, lowest power programmable SRIO solution in the industry.
Lattice has licensed the IP core from Praesum and has full rights to use and sub-license the Serial RapidIO IP core.
RapidIO has won broad acceptance in wireless infrastructure applications, where it is used as a primary interconnect for DSP clusters in baseband processing. In the past, vendors had to rely on expensive, premium FPGAs for these applications. However, the combination of the Serial RapidIO 2.1 core and the LatticeECP3 FPGA will allow customers to develop low-power infrastructure solutions for 3G, LTE and WiMAX without sacrificing performance or cost. The Serial RapidIO 2.1 core and other Lattice IP cores such as low latency CPRI and GbE/SGMII comprise a comprehensive IP suite in support of wireless infrastructure applications.
"As the only supplier of fully compliant RapidIO 2.1 IP, Praesum's partnership with Lattice will help to accelerate deployment of this next generation technology in high performance signal processing applications. When combined with our RapidIO 2.1 switching IP, the endpoint IP for the LatticeECP3 FPGA represents a complete solution for wireless infrastructure equipment vendors," said Kent Dahlgren, Praesum's CEO.
"Our partnership with Praesum has yielded the first programmable Serial RapidIO 2.1 endpoint solution, and an interoperability ecosystem that will dramatically reduce cost and power for wireless infrastructure manufacturers," said Shakeel Peera, Lattice's Director of Marketing for SRAM FPGAs.
Praesum is a leader in RapidIO switching, bridging, and endpoint IP. The company's small footprint Serial RapidIO 2.1 IP core can be used for processor bridging, control plane interfaces and bridging to legacy interfaces. The core architecture for the Serial RapidIO 2.1 IP core includes the following features:
- Allows for 1x, 2x, 4x lane configurations
- Up to 3.125Gbps
- Implements physical layer, transport layer, maintenance transaction handling and error management extensions.
- Provides infrastructure support for external logical layer functions, enabling maximum flexibility
- Provides a choice of logical layer functions that are important for the application
- Provides a choice of how logic layer functions interact with the rest of the system - SOC bus or streaming interfaces.
- Supports software implementations of control plane oriented functions such as doorbells and messages
- Backward compatible with the v1.3 specification
The LatticeECP3 FPGA family is comprised of five devices that offer standards-compliant multi-protocol 3.2G SERDES, DDR1/2/3 memory interfaces for low cost FPGAs and high performance, cascadable DSP slices that are ideal for high performance RF, baseband and image signal processing. Toggling at 1 Gbps, the LatticeECP3 FPGAs also feature the fastest LVDS I/O available in a mid-range FPGA family, as well as embedded memory of up to 6.8 Mbits. Logic density varies from 17K LUTs to 149K LUTs with up to 586 user I/O. The LatticeECP3 FPGA family is ideally suited for deployment in high volume cost- and power-sensitive wireless infrastructure and wireline applications.
The Serial RapidIO 2.1 IP core is available for immediate customer evaluation and use.
Serial RapidIO 2.1 IP core