SAN FRANCISCOLattice Semiconductor Corp. and partner Praesum Communications Monday (Nov. 23) announced the availability of the Serial RapidIO 2.1 endpoint soft IP core for the LatticeECP3 FPGA family.
The core supports 1x, 2x and 4x lane configurations at up to 3.125Gbps lane speeds, Lattice (Hillsboro, Ore.) said. Lattice said it licensed this IP core from Praesum (Petaluma, Calif.) and has full rights to use and sub-license the Serial RapidIO IP core.
According to Lattice, the combination of the Serial RapidIO 2.1 core and the LatticeECP3 FPGA will allow customers to develop low-power infrastructure solutions for 3G, LTE and WiMAX without relying on expensive, premium FPGAs. LatticeECP3-70 devices are priced as low as $35 in high volumes.
The Serial RapidIO 2.1 core and other Lattice IP cores such as low latency CPRI and GbE/SGMII comprise a comprehensive IP suite in support of wireless infrastructure applications, according to Lattice.
Lattice said the core architecture for the Serial RapidIO 2.1 IP core includes the following features:
Allows for 1x, 2x, 4x lane configurations
Up to 3.125Gbps
Implements physical layer, transport layer, maintenance transaction
handling and error management extensions
Provides infrastructure support for external logical layer functions, enabling maximum flexibility
Provides a choice of logical layer functions that are important for
Provides a choice of how logic layer functions interact with the rest
of the system -- SOC bus or streaming interfaces
Supports software implementations of control plane oriented functions such as doorbells and messages
Backward compatible with the v1.3 specification
More information about the core is available on the Lattice website.