SAN FRANCISCOEDA vendor Aldec Corp. Monday (Dec. 21) released its latest RTL and gate-level simulator, Active-HDL 8.2 sp1, for FPGA design and verification engineers.
According to Aldec (Henderson, Nev.), Active-HDL 8.2 sp1 includes full support for Xilinx SecureIP, IEEE VHDL/Verilog-encrypted IP and an enhanced assertions bundle option.
The new assertion bundle supports three assertion types: IEEE 1800 SystemVerilog assertions (SVA), property description language (PSL) and Open Vera assertions (OVA) for legacy designs, Alec said. The bundle also supports a dedicated assertions viewer, assertion debugging and complete visibility of assertions, properties and functional coverage statements through the simulator, Aldec said.
Active-HDL 8.2 sp1 is available immediately and sold directly from Aldec and its authorized world-wide distributors, the company said. Pricing information was not provided. More information about the product is available through Aldec's website.