Santa Clara, Calif. - Tensilica, Inc.'s third generation of Diamond Standard controllers comprises five upward-compatible processor cores based on a common Xtensa architecture. The new controllers deliver up to 15 percent faster clock speed, up to 20 percent smaller die area and up to 15 percent less power consumption. They are targeted for a wide range of embedded control functions in compute-intensive dataplane functions.
"The Diamond processor family provides our customers with significant improvements in speed/power performance in the widest range of fully compatible 32-bit controllers in the industry," stated Steve Roddy, Tensilica's vice president of marketing and business development. "These deeply embedded control cores can also serve as a starting point for customization of a tailored Xtensa dataplane processor (DPU) for designers looking to incorporate additional control or signal processing capability."
The ultra-low-power Diamond 106Micro is a small cache-less controller with memory protection, an iterative 32x32 multiplier, 15 interrupts, an integrated timer, and on-chip debug hardware that achieves Dhrystone 2.1 results of 1.22 DMIPS/MHz.
The small Diamond 108mini adds a 32-bit integer divider, dual local data RAMs, 22 interrupts, three integrated timers, and dual 32-bit GPIO (general-purpose input/output) ports. It achieves Dhrystone 2.1 results of 1.34 DMIPS/MHz.
The Diamond 212GP adds data and instruction caches and 16-bit DSP instructions, and achieves Dhrystone 2.1 results of 1.38 DMIPS/MHz.
The Diamond 233L has the same features as a Diamond 212GP and adds a Memory Management Unit (MMU) optimized for Linux operating systems.
The ultra-high-performance Diamond 570T is a three-issue VLIW (very long instruction word) core with dual 32x32 MULs and 16 Kbyte, 2-way set associative instruction and data caches, and achieves Dhrystone 2.1 results of 1.59 DMIPS/MHz.
The Diamond Standard processors were designed with easy SOC (system on chip) integration in mind. All of the Diamond controllers are available with support for AMBA AHB-Lite and AXI bridges with asynchronous or synchronous clocks. In addition, on the Diamond 108Mini, 212GP, and 570T, designers can bypass the system bus altogether in order to achieve much higher input/output I/O bandwidth and seamless integration with RTL via direct GPIO connection interfaces for data and system monitoring and control. The Diamond 570T also provides 32-bit FIFO interfaces for direct data I/O (input/output) interface with other system blocks without using the system bus.
The Diamond Standard processors are available now.
For more information visit www.tensilica.com.