LONDON Processor IP company MIPS Technologies Inc. (Sunnyvale, Calif.) is teaming up with another IP licensor Virage Logic Corp. (Fremont, Calif.) to offer embedded memoryIP for joint customers.
Virage has SRAM compilers optimized for MIPS32 processors at the 90-nm and 65-nm nodes The ASAP 90-nm and SiWare 65GP SRAM instances were jointly developed by MIPS and Virage Logic for the 4KE, 24K), 24KE, 34K, 74K and 1004K processor core families. Each Virage Logic ASAP and SiWare Memory High Density SRAM instance is offered at a special price compared to a full-featured SRAM compiler. Additional instances and full featured compilers are also available.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.