PARIS EDA and IP vendor Synopsys Inc. (Mountain View, Calif.) said it has extended its topographical technology in Design Compiler 2010 to produce physical guidance to its place-and-route solution, IC Compiler.
Introduced earlier this week, Synopsys' Design Compiler 2010 is claimed to achieve a two-fold speedup in the synthesis and physical implementation flow.
In a discussion with EDA DesignLine, Gal Hasson, senior director of marketing, RTL synthesis, power and test automation at Synopsys, provided details on the topographical technology and in what respect it has been extended to help designers shorten design cycles and improve productivity.
The topographical technology was introduced into Design Compiler in 2005 when Synopsys brought some physical technology from IC Compiler into Design Compiler and eliminated the use of wireload models to estimate wire capacitance and delays in synthesis, Hasson explained.
Instead, he continued, actual physical information was used to estimate wire delays, leading to 10 percent timing, area and power correlation between Design Compiler and IC Compiler. "In 2008, we extended topographical technology to predict, visualize and fix routing congestion during synthesis."
With Design Compiler 2010, Hasson claimed that the topographical technology has been further extended in various ways. Firstly, coupling capacitance and interconnect delay modeling have been enhanced to take cell density into account, resulting in a more accurate model, he noted.
Secondly, Hasson outlined that physical optimizations "never before performed in synthesis" are introduced in Design Compiler 2010. For instance, he indicated that timing-driven placement optimizations result in a better starting point for place and route.
Moving to the third enhancement, Hasson said physical guidance is generated and passed from Design Compiler 2010 to IC Compiler to seed its placement, resulting in a better starting point for place and route, 1.5x faster placement runtime in IC Compiler, and Design Compiler's timing and area results being within 5 percent of IC Compiler results.